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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com st16c554/554d 2.97v to 5.5v quad uart with 16-byte fifo june 2006 rev. 4.0.1 general description the st16c554/554d (554) is a quad universal asynchronous receiver and transmitter (uart) with 16 bytes of transmit and receive fifos, selectable receive fifo trigger levels and data rates of up to 1.5 mbps. each uart has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. an internal loopback capability allows onboard diagnostics. the 554 is available in a 64-pin lqfp and a 68-pin plcc package. the 64-pin package only offers the 16 mode interface, but the 68-pin package offers an additional 68 mode interface which allows easy integration with motorola processors. the st16c554cq64 (64-pin) offers three state interrupt output while the st16c554dcq64 provides continuous interrupt output. the 554 combines the package interface modes of the 16c554 and 68c554 on a single integrated chip. features ? pin-to-pin compatible wit h the industry standard st16c454, st68c454, st68c554, ti?s tl16c554a and philips? sc16c554b ? intel or motorola data bus interface select ? four independent uart channels register set compatible to 16c550 data rates of up to 1.5 mbps at 5 v data rates of up to 500 kbps at 3.3v 16 byte transmit fifo 16 byte receive fifo with error tags 4 selectable rx fifo trigger levels full modem interface ? 2.97v to 5.5v supply operation ? crystal oscillator or external clock input applications ? portable appliances ? telecommunication network routers ? ethernet network routers ? cellular data devices ? factory automation and process controls f igure 1. st16c554 b lock d iagram xtal1 xtal2 crystal osc / buffer data bus interface uart channel a 16 byte tx fifo 16 byte rx fifo brg ir endec tx & rx uart regs 2. 97 v to 5.5 v vcc gnd txb, rxb, irtxb, dtrb#, dsrb#, rtsb#, ctsb#, cdb#, rib# uart channel b (same as channel a) a2:a0 d7:d0 csa# 16 / 68# csb# inta intb iow# ior# reset intsel txrdy# a-d rxrdy# a-d uart channel c (same as channel a) txa, rxa, irtxa, dtra#, dsra#, rtsa#, ctsa#, cda#, ria# txc, rxc, irtxc, dtrc#, dsrc#, rtsc#, ctsc#, cdc#, ric# uart channel d (same as channel a) txd, rxd, irtxd, dtrd#, dsrd#, rtsd#, ctsd#, cdd#, rid# csc# csd# intc intd
st16c554/554d 2 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 f igure 2. p in o ut a ssignment ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus st16c554cq64 64-lead lqfp 0c to +70c active st16c554dcq64 64-lead lqfp 0c to +70c active st16c554diq64 64-lead lqfp -40c to +85c active st16c554dcj68 68-lead plcc 0c to +70c active st16c554dij68 68-lead plcc -40c to +85c active st68c554cj68 68-lead plcc 0c to +70c active st68c554ij68 68-lead plcc -40c to +85c active 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dsra# ctsa# dtra# vcc rtsa# inta csa# txa iow# txb csb# intb rtsb# gnd dtrb# ctsb# dsrb# cdb# rib# rxb vcc 16/68# a2 a1 a0 xtal1 xtal2 reset rxrdy# txrdy# gnd rxc ric# cdc# dsrd# ctsd# dtrd# gnd rtsd# intd csd# txd ior# txc csc# intc rtsc# vcc dtrc# ctsc# dsrc# cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc rxd rid# cdd# st16c554 68-pin plcc intel mode (16/68# pin connected to vcc) 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dsra# ctsa# dtra# vcc rtsa# irq# cs# txa r/w# txb a3 n.c. rtsb# gnd dtrb# ctsb# dsrb# cdb# rib# rxb vcc 16/68# a2 a1 a0 xtal1 xtal2 reset rxrdy# txrdy# gnd rxc ric# cdc# dsrd# ctsd# dtrd# gnd rtsd# n.c. n.c. txd n.c. txc a4 n.c. rtsc# vcc dtrc# ctsc# dsrc# cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 gnd vcc rxd rid# cdd# st16c554 68-pin plcc motorola mode (16/68# pin connected to gnd) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dsra# ctsa# dtra# vcc rtsa# inta csa# txa iow# txb csb# intb rtsb# gnd dtrb# ctsb# dsrb# cdb# rib# rxb vcc a2 a1 a0 xtal1 xtal2 reset gnd rxc ric# cdc# dsrc# dsrd# ctsd# dtrd# gnd rtsd# intd csd# txd ior# txc csc# intc rtsc# vcc dtrc# ctsc# cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 vcc rxd rid# cdd# st16c554/554d 64-pin tqfp intel mode only 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dsra# ctsa# dtra# vcc rtsa# irq# cs# txa r/w# txb a3 n.c. rtsb# gnd dtrb# ctsb# dsrb# cdb# rib# rxb vcc gnd a2 a1 a0 xtal1 xtal2 reset rxrdy# txrdy# gnd rxc ric# cdc# dsrd# ctsd# dtrd# gnd rtsd# n.c. n.c. txd n.c. txc a4 n.c. rtsc# vcc dtrc# ctsc# dsrc# cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 gnd vcc rxd rid# cdd# st68c554 68-pin plcc motorola mode only
st16c554/554d 3 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo pin descriptions pin description n ame 64-lqfp p in # 68-plcc p in # t ype d escription data bus interface a2 a1 a0 22 23 24 32 33 34 i address data lines [2:0]. these 3 address lines select one of the internal regis - ters in uart channel a-d during a data bus transaction. d7 d6 d5 d4 d3 d2 d1 d0 60 59 58 57 56 55 54 53 5 4 3 2 1 68 67 66 i/o data bus lines [7:0] (bidirectional). ior# (vcc) 40 52 i when 16/68# pin is high, the intel bus interface is selected and this input becomes read strobe (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [a2:a0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. when 16/68# pin is low, the motorola bus interface is selected and this input is not used and should be connected to vcc. iow# (r/w#) 9 18 i when 16/68# pin is high, it selects intel bus interface and this input becomes write strobe (active low). the falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. when 16/68# pin is low, the motorola bus interface is selected and this input becomes read (high) and write (low) signal. csa# (cs#) 7 16 i when 16/68# pin is high, this input is ch ip select a (active low) to enable chan - nel a in the device. when 16/68# pin is low, this input becomes the chip select (active low) for the motorola bus interface. csb# (a3) 11 20 i when 16/68# pin is high, this input is ch ip select b (active low) to enable chan - nel b in the device. when 16/68# pin is low, this input becomes address line a3 which is used for channel selection in the motorola bus interface. csc# (a4) 38 50 i when 16/68# pin is high, this input is chip select c (active low) to enable chan - nel c in the device. when 16/68# pin is low, this input becomes address line a4 which is used for channel selection in the motorola bus interface. csd# (vcc) 42 54 i when 16/68# pin is high, this input is chip select d (active low) to enable chan - nel d in the device. when 16/68# pin is low, this input is not used and should be connected vcc.
st16c554/554d 4 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 inta (irq#) 6 15 o (od) when 16/68# pin is high for intel bus interface, this ouput becomes channel a interrupt output. the output state is defined by the user and through the soft - ware setting of mcr[3]. inta is set to the active mode when mcr[3] is set to a logic 1. inta is set to the three state mode when mcr[3] is set to a logic 0 (default). see mcr[3]. when 16/68# pin is low for motorola bus interface, this output becomes device interrupt output (active low, open drain). an external pull-up resistor is required for proper operation. intb intc intd (n.c.) 12 37 43 21 49 55 o when 16/68# pin is high for intel bus interface, these ouputs become the inter - rupt outputs for channels b, c, and d. the output state is defined by the user through the software setting of mcr[3]. the interrupt outputs are set to the active mode when mcr[3] is set to a logic 1 and are set to the three state mode when mcr[3] is set to a l ogic 0 (default). see mcr[3]. when 16/68# pin is low for motorola bu s interface, these outputs are unused and will stay at logic zero level. leave these outputs unconnected. intsel - 65 i interrupt select (active high, input with internal pull-down). when 16/68# pin is high for intel bus interface, this pin can be used in conjunc - tion with mcr bit-3 to enable or disable the int a-d pins or override mcr bit-3 and enable the interrupt outputs. inte rrupt outputs are enabled continuously when this pin is high. mcr bit-3 enables and disables the interrupt output pins. in this mode, mcr bit-3 is set to a logic 1 to enable the continuous output. see mcr bit-3 description for full detail. this pin must be low in the motorola bus interface mode. for the 64 pin packages, this pin is bonded to vcc inter - nally in the st16c554dcq64 so the int outputs operate in the continuous interrupt mode. this pin is bonded to gnd internally in the st16c554cq64 and therefore requires settin g mcr bit-3 for enabling the interrupt output pins. txrdy# - 39 o transmitter ready (active low). this out put is a logically anded status of txrdy# a-d. see ta b l e 5 . if this output is unu sed, leave it unconnected. rxrdy# - 38 o receiver ready (active low). this output is a logically anded status of rxrdy# a-d. see table 5 . if this output is unused, leave it unconnected. modem or serial i/o interface txa txb txc txd 8 10 39 41 17 19 51 53 o uart channels a-d transmit data and infr ared transmit data. in this mode, the tx signal will be high during reset, or idle (no data). rxa rxb rxc rxd 62 20 29 51 7 29 41 63 i uart channel a-d receive data. normal receive data input must idle high. rtsa# rtsb# rtsc# rtsd# 5 13 36 44 14 22 48 56 o uart channels a-d request-to-send (active low) or general purpose output. if these outputs are not used, leave them unconnected. ctsa# ctsb# ctsc# ctsd# 2 16 33 47 11 25 45 59 i uart channels a-d clear-to-send (active lo w) or general purpose input. these inputs should be connected to vcc when not used. pin description n ame 64-lqfp p in # 68-plcc p in # t ype d escription
st16c554/554d 5 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo pin type: i=input, o=output, i/o= input/output, od=output open drain. dtra# dtrb# dtrc# dtrd# 3 15 34 46 12 24 46 58 o uart channels a-d data-terminal-ready (active low) or general purpose out - put. if these outputs are not used, leave them unconnected. dsra# dsrb# dsrc# dsrd# 1 17 32 48 10 26 44 60 i uart channels a-d data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. cda# cdb# cdc# cdd# 64 18 31 49 9 27 43 61 i uart channels a-d carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. ria# rib# ric# rid# 63 19 30 50 8 28 42 62 i uart channels a-d ring-indicator (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. ancillary signals xtal1 25 35 i crystal or external clock input. xtal2 26 36 o crystal or buffered clock output. 16/68# - 31 i intel or motorola bus select (input with internal pull-up). when 16/68# pin is high, 16 or intel mo de, the device will operate in the intel bus type of interface. when 16/68# pin is low, 68 or motorola mode, the device will operate in the motorola bus type of interface. motorola bus interface is not available on the 64 pin package. reset (reset#) 27 37 i when 16/68# pin is high for intel bus interface, this input becomes the reset pin (active high). in this case, a 40 ns minimum high pulse on this pin will reset the internal registers and all outputs. the uart transmitter output will be held high, the receiver input will be ignored and outputs are reset during reset period ( ta b l e 13 ). when 16/68# pin is at low for motorola bus interface, this input becomes reset# pin (active low). this pin functions similarly, but instead of a high pulse, a 40 ns minimum low pulse will reset the internal registers and outputs. motorola bus interface is not available on the 64 pin package. vcc 4, 21, 35, 52 13, 30, 47, 64 pwr 2.97v to 5.5v power supply. gnd 14, 28, 45, 61 6, 23, 40, 57 pwr power supply common, ground. n.c. - - no connection. these pins are not used in either the intel or motorola bus modes. pin description n ame 64-lqfp p in # 68-plcc p in # t ype d escription
st16c554/554d 6 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 1.0 product description the st16c554 (554) integrates the functions of 4 enhanced 16c550 universal asynchrounous receiver and transmitter (uart). each uart is independently cont rolled and has its own set of device configuration registers. the configuration registers set is 16550 ua rt compatible for control, status and data transfer. additionally, each uart channel has 16 bytes of transmit and receive fifos, programmable baud rate generator and data rate up to 1.5 mbps at 5v. the st16c554 can operate from 2.97 to 5.5 volts. the 554 is fabricated with an advanced cmos process. enhanced fifo the 554 quart provides a solution that supports 16 byte s of transmit and receive fifo memory, instead of one byte in the st16c454. the 554 is designed to wo rk with high performance da ta communication systems, that require fast data processing time. increased performa nce is realized in the 554 by the larger transmit and receive fifos and receiver fifo trig ger level control. this allows the external processor to handle more networking tasks within a given time. th is increases the service interval givi ng the external cpu additional time for other applications and reducing the overall uart interrupt servicing time. data bus interface, intel or motorola type the 554 provides a single host interface for all 4 uarts and supports intel or motorola microprocessor (cpu) data bus interface. the intel bus compatible interface a llows direct interconnect to intel compatible type of cpus using ior#, iow# and csa#, csb#, csc# and csd# inputs for data bus operation. the motorola bus compatible interface instead uses th e r/w#, cs#, a3 and a4 signals for data bus transactions. few data bus interface signals change their functions depending on user?s selection, see pin description for details. the intel and motorola bus interface selection is made th rough the 16/68# (pin 31 of the plcc package). data rate the 554 is capable of operation up to 1.5 mbps at 5v. the device can operate at 5v with a crystal or external clock of up to 24 mhz. with a typical crystal of 14. 7456 mhz and through a software option, the user can set the sampling rate for data rates of up to 921.6 kbps. enhanced features the rich feature set of the 554 is ava ilable through the internal registers. selectable rece ive fifo trigger levels, programmable baud rates, infrared encoder/decoder inte rface and modem interface controls are all standard features. in the 16 mode intsel and mcr bit-3 can be configured to provide a software controlled or continuous interrup t capability. for backward co mpatibility to the st16 c554, the 64-pin lq fp does not have the intsel pin. instead, two different lqfp packa ges are offered. the st16c554div operates in the continuous interrupt enable mode by internally bond ing intsel to vcc. the st16c554iv operates in conjunction with mcr bit-3 by internally bonding intsel to gnd.
st16c554/554d 7 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the 554 data interface supports the inte l compatible types of cpus and it is compatible to the industry standard 16c550 uart. no clock (oscillator nor external clock) is required for a data bus transaction. each bus cycle is asynchronous using cs# a- d, ior# and iow# or cs#, r/w#, a4 and a3 inputs. all four uart channels share the same data bus for host operations. a typical data bus interconnection for intel and motorola mode is shown in figure 3 . f igure 3. st16c554 t ypical i ntel /m otorola d ata b us i nterconnections vcc vcc dsra# ctsa# rtsa# dtra# rxa txa ria# cda# gnd a0 a1 a2 uart_csa# uart_csb# ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_intb uart_inta intb inta uart_reset reset serial interface of rs-232 serial interface of rs-232 intel data bus (16 mode) interconnections uart channel c uart channel d similar to ch a similar to ch a similar to ch a uart_intd uart_intc intd intc uart_csc# uart_csd# csc# csd# vcc 16/68# vcc vcc gnd a0 a1 a2 uart_cs# a3 r/w# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart_irq# intb inta reset# serial interface of rs-232 serial interface of rs-232 motorola data bus (68 mode) interconnections vcc uart_reset# (no connect) dsra# ctsa# rtsa# dtra# rxa txa ria# cda# uart channel a uart channel b uart channel c similar to ch a similar to ch a similar to ch a intc (no connect) intd (no connect) a4 csc# csd# vcc 16/68# uart channel d vcc
st16c554/554d 8 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 2.2 device reset the reset input resets the internal r egisters and the serial interface output s in all channels to their default state (see ta b l e 13 ). an active high pulse of lo nger than 40 ns dura tion will be required to activate the reset function in the device. following a po wer-on reset or an external reset, the 554 is software compatible with previous generation of uarts, 16c454 and 16c554. 2.3 channel selection the uart provides the user with the capability to bi-directionally tr ansfer information be tween an external cpu and an external serial communication device. during intel bus mode (16/68# pin is connected to vcc), a logic 0 on chip select pins, csa#, csb#, csc# or csd# allows the user to select uart channel a, b, c or d to configure, send transmit data and/or unload receiv e data to/from the uart. selecting all four uarts can be useful during power up initialization to write to the same internal registers, but do not attempt to read from all four uarts simultaneously. individual channel select functions are shown in table 1 . during motorola bus mode (16/68# pin is connected to gnd), the package interface pins are configured for connection with motorola, and other popular microproce ssor bus types. in this mode the 554 decodes two additional addresses, a3 and a4, to select one of the four uart ports. the a3 and a4 address decode function is used only when in the motorola bus mode. see table 2 . t able 1: c hannel a-d s elect in 16 m ode csa# csb# csc# csd# f unction 1 1 1 1 uart de-selected 0 1 1 1 channel a selected 1 0 1 1 channel b selected 1 1 0 1 channel c selected 1 1 1 0 channel d selected 0 0 0 0 channels a-d selected t able 2: c hannel a-d s elect in 68 m ode cs# a4 a3 f unction 1 x x uart de-selected 0 0 0 channel a selected 0 0 1 channel b selected 0 1 0 channel c selected 0 1 1 channel d selected
st16c554/554d 9 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo 2.4 channels a-d internal registers each uart channel in the 554 has a set of enhanced re gisters for controlling, monitoring and data loading and unloading. the configuration register set is compatib le to those already available in the standard single 16c550. these registers function as data holding regist ers (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and control registers (lsr/lcr), modem status and control registers (msr/mcr), programmable data rate (clock) divisor register s (dll/dlm), and a user accessible scratchpad register (spr). all the register functions are discussed in full detail later in ?section 3.0, uart internal registers? on page 15 . 2.5 int ouputs for channels a-d the interrupt outputs change according to the operating mode and enhanced features setup. table 3 and 4 summarize the operating behavior for the transmitter and receiver. also see figure 17 through 22 . 2.6 dma mode the device does not support direct memory access. th e dma mode (a legacy term) in this document does not mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# a-d and txrdy# a-d output pins. the tran smit and receive fifo trigger levels provide additional flexibility to the user fo r block mode operation. the lsr bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for mo re data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3 = 1). when the transmit and receive fifos are enabled and the dma mode is disabled (fcr bit-3 = 0), the 554 is placed in single-character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by t able 3: int p in o peration for t ransmitter for c hannels a-d fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) int pin low = a byte in thr high = thr empty low = fifo above trigger level high = fifo below trigger level or fifo empty low = fifo above trigger level high = fifo below trigger level or fifo empty t able 4: int p in o peration for r eceiver for c hannels a-d fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) int pin low = no data high = 1 byte low = fifo below trigger level high = fifo above trigger level low = fifo below trigger level high = fifo above trigger level
st16c554/554d 10 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 loading or unloading the fifo in a block sequence det ermined by the programmed trigger level. the following table show their behavior. also see figure 17 through 22 . 2.7 crystal oscillator or external clock input the 554 includes an on-chip oscillato r (xtal1 and xtal2) to produce a clock for both uart sections in the device. the cpu data bus does not require this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal 2 pin being the output. fo r programming details, see ?section 2.8, programmable baud rate generator? on page 10 . the on-chip oscillator is designed to use an industry standard micropro cessor crystal (p arallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connec ted externally be tween the xtal1 and xtal2 pins. typical oscillator connections are shown in figure 4 . alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for stan dard or custom rates. for further reading on oscillator ci rcuit please see application note dan108 on exar?s web site. 2.8 programmable baud rate generator each uart has its own baud rate generator (brg) for the transmitter and receiver. the brg further divides this clock by a programmable divisor between 1 and (2 16 - 1) to obtain a 16x sampling rate clock of the serial data rate. the sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor is unknown (dll = 0xxx and dlm = 0xxx) and should be initialized after power up. programming the ba ud rate generator regi sters dll and dlm provides t he capability for selecting the operating data rate. table 6 shows the standard data rates available with a 14.7456mhz crystal or external clock. t able 5: txrdy# and rxrdy# o utputs in fifo and dma m ode for c hannels a-d p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr b it -3 = 0 (dma m ode d isabled ) fcr b it -3 = 1 (dma m ode e nabled ) rxrdy# low = 1 byte high = no data low = at least 1 byte in fifo high = fifo empty high to low transition when fifo reaches the trigger level, or timeout occurs low to high transition when fifo empties txrdy# low = thr empty high = byte in thr low = fifo empty high = at least 1 byte in fifo low = fifo has at least 1 empty location high = fifo is full f igure 4. t ypical c rystal c onnections c1 22-47pf c2 22-47pf 14.7456 mhz xtal1 xtal2 r=300k to 400k
st16c554/554d 11 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo 2.9 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 16 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal sampling clock. a bit time is 16x clock periods. the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and a dds the stop-bit(s). the stat us of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.9.1 transmit holding regi ster (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 16 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. f igure 5. b aud r ate g enerator t able 6: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 (d efault ) d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0 xtal1 xtal2 crystal osc/ buffer dll and dlm registers 16 x sampling rate clock to transmitter and receiver to other channels programmable baud rate generator logic
st16c554/554d 12 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 2.9.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a tr ansmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. 2.9.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 16 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the fifo becomes empty. the transmit empty interrupt is e nabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. 2.10 receiver the receiver section contains an 8-bit receive shift register (rsr) and 16 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x clock for timing. it verifies and validates every bit on the incoming char acter in the middle of each da ta bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x clock rate. after 8 clocks the start bit period should be at the center of the start bit. at this ti me the start bit is sampled and if it is still low it is validated. evaluating the start bit in this manner prevents the receiver from as sembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error tags are immediatel y updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo trigger level. furthe rmore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word leng ths as defined by lcr[1:0] pl us 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. see figure 8 and figure 9 . f igure 6. t ransmitter o peration in non -fifo m ode f igure 7. t ransmitter o peration in fifo m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock transmit data shift register ( tsr ) transmit data byte thr interrupt (isr bit-1) when the tx fifo becomes empty. fifo is enabled by fcr bit-0 =1. transmit fifo 16x clock txfifo1
st16c554/554d 13 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo 2.10.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 16 bytes by 11-bit wide, the 3 extra bits are for the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 8. r eceiver o peration in non -fifo m ode f igure 9. r eceiver o peration in fifo receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2 receive data shift register (rsr) rxfifo1 16x clock error tags (16-sets) error tags in lsr bits 4:2 receive data characters data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 asking for stopping data when data fills above the flow control trigger level to suspend remote transmitter. asking for sending data when data falls below the flow control trigger level to restart remote transmitter. 16 bytes by 11-bit wide fifo fifo trigger=8 data falls to 4 data fills to 14 example : - rx fifo trigger level selected at 8 bytes (see note below)
st16c554/554d 14 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 2.11 internal loopback the 554 uart provides an internal loopback capability for system di agnostic purposes. t he internal loopback mode is enabled by setting mcr register bit-4 to logic 1. all regular uart functions operate normally. figure 10 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held high or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input must be held high during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. f igure 10. i nternal l oop b ack in c hannel a and b tx a-d rx a-d modem / general purpose control logic internal data bus lines and control signals rts# a-d mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) cts# a-d dtr# a-d dsr# a-d ri# a-d cd# a-d op1# op2# rts# cts# dtr# dsr# ri# cd# vcc
st16c554/554d 15 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo 3.0 uart internal registers each uart channel in the 554 has its own set of configuration registers selected by address lines a0, a1 and a2 with a specific channel selected (see table 1 and table 2 ). the complete register set is shown on table 7 and table 8 . t able 7: uart channel a and b uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - divisor lsb read/write lcr[7] = 1 0 0 1 dlm - divisor msb read/write 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr[7] = 0 1 0 1 lsr - line status register read-only 1 1 0 msr - modem status register read-only 1 1 1 spr - scratch pad register read/write
st16c554/554d 16 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 12. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 11. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). t able 8: internal registers description. a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0 0 0 0 modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable 0 1 0 isr rd fifos enabled fifos enabled 0 0 int source bit-3 int source bit-2 int source bit-1 int source bit-0 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0 0 dma mode enable tx fifo reset rx fifo reset fifos enable 0 1 1 lcr rd/wr divisor enable set tx break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0 0 0 internal lopback enable int output enable (op2#) rsvd (op1#) rts# output control dtr# output control lcr[7] = 0 1 0 1 lsr rd/wr rx fifo global error thr & tsr empty thr empty rx break rx framing error rx parity error rx over - run error rx data ready 1 1 0 msr rd/wr cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
st16c554/554d 17 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive interr upts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; resetting ier bits 0-3 enables the st16c554 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data characte r in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready in terrupt which is issued whenever t he thr becomes empty. if the thr is empty when this bit is enabled , an interrupt will be generated. ? logic 0 = disable transmit ready interrupt (default). ? logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo . lsr bit-1 generates an interrupt immediately when an overrun occurs. lsr bits 2-4 generate an interrupt when the character in the rhr has an error. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[7:4]: reserved (default 0)
st16c554/554d 18 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 4.4 interrupt status register (isr) the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt le vel to be serviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 9 , shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by thr empty (non-fifo mode) or tx fifo empty (fifo mode). ? msr is by any of the msr bits 0, 1, 2 and 3. 4.4.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register. ? rxrdy interrupt is cleared by reading data until fifo falls be low the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr. ? txrdy interrupt is cleared by a read to the isr register or by writing to thr. ? msr interrupt is cleared by a read to the msr register. ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents may be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority leve ls (see interrupt source table 9 ). isr[5:4]: reserved (default 0) isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -3 b it -2 b it -1 b it -0 1 0 1 1 0 lsr (receiver line status register) 2 1 1 0 0 rxrdy (receive data time-out) 3 0 1 0 0 rxrdy (received data ready) 4 0 0 1 0 txrdy (transmit empty) 5 0 0 0 0 msr (modem status register) - 0 0 0 1 none (default)
st16c554/554d 19 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fi fos, set the receive fifo tr igger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default). ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see dma operation section for details. ? logic 0 = normal operation (default). ? logic 1 = dma mode. fcr[5:4]: reserved (default 0) fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in the fifo crosses the trigger level. table 10 shows the comple te selections. t able 10: r eceive fifo t rigger l evel s election fcr b it -7 fcr b it -6 r eceive t rigger l evel 0 0 1 1 0 1 0 1 1 4 8 14
st16c554/554d 20 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 11 for parity select ion summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2
st16c554/554d 21 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to high for th e transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bi t is forced to low for th e transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space?, logic 0, state). this co ndition remains, until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition. (default) ? logic 1 = forces the transmitter output (tx) to a ?space ?, logic 0, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for controlling the serial/mod em interface signals or g eneral purpose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output high (default). ? logic 1 = force dtr# output low. mcr[1]: rts# output the rts# pin is a modem control output. if the modem in terface is not used, this output may be used as a general purpose output. ? logic 0 = force rts# output high (default). ? logic 1 = force rts# output low. mcr[2]: reserved op1# is not available as an output pin on the 554. but it is available for use during internal loopback mode. in the loopback mode, this bit is used to write the state of the modem ri# interface signal. t able 11: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, high 1 1 1 forced parity to space, low
st16c554/554d 22 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 mcr[3]: int output enable enable or disable int outputs to become active or in thre e-state. this function is associated with the intsel input, see below table for details. th is bit is also used to control the op2# signal during internal loopback mode. intsel pin must be low during 68 mode. ? logic 0 = int (a-d) outputs disabled (three state) in the 16 mode (default). during internal loopback mode, op2# is high. ? logic 1 = int (a-d) outputs enabled (active) in the 16 mode. during internal loopback mode, op2# is low. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 10 . mcr[7:5]: reserved (default 0) 4.8 line status register (lsr) - read/write this register is writeable but it is not recommended. th e lsr provides the status of data transfers between the uart and the host. if ier bit-2 is enabled, lsr bit-1 will generate an interrupt immediately and lsr bits 2-4 will generate an inte rrupt when a char acter with an error is in the rhr. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and can be read from the receive holding register or rx fifo. lsr[1]: receiver overrun flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error tag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct pa rity information and is suspect. this error is associated with the char acter available for reading in rhr. lsr[3]: receive data framing error tag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. t able 12: int o utput m odes intsel p in mcr b it -3 int a-d o utputs in 16 m ode 0 0 three-state 0 1 active 1 x active
st16c554/554d 23 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo lsr[4]: receive break tag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx wa s low for at least one char acter frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, ?mark? or high. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. t he bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bi t is set to a logic 1 whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears wh en there is no more error(s) in any of the bytes in the rx fifo. 4.9 modem status register (msr) - read/write this register is writeable but it is not recommended. the msr provi des the current state of the modem interface input signals. lower four bits of this register are used to indica te the changed information. these bits are set to a logic 1 whenever a signal from the mode m changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from low to high, ending of the ringing signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3).
st16c554/554d 24 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 msr[4]: cts input status a high on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a low will resume data transmission. normally msr bit-4 bit is the compliment of the cts# input. however in the loopback mode, this bit is equivale nt to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the complement of the dsr# input. in the loopback mode , this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# input. in the loopback mode th is bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. 4.11 baud rate generator registers (dll and dlm) - read/write these registers make-up the value of the baud rate divisor. the concatenation of the contents of dlm and dll gives the 16-bit divisor value. see ?section 2.8, programmable baud rate generator? on page 10.
st16c554/554d 25 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo t able 13: uart reset condit ions for channels a-d registers reset state dlm, dll dlm and dll are unknown upon power up. they do not reset when the reset pin is asserted. rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff i/o signals reset state tx high irtx low rts# high dtr# high rxrdy# high txrdy# low int (16 mode) st16c554 = three-state condition (intsel = low) st16c554 = low (intsel = high) st16c554d = low irq# (68 mode) high (intsel = low)
st16c554/554d 26 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 absolute maximum ratings power supply range 7 volts voltage at any pin gnd-0.3 v to vcc+0.3 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data (margin of error: 15%) thermal resistance (64-lqfp) theta-ja = 50 o c/w, theta-jc = 11 o c/w thermal resistance (68-plcc) theta-ja = 46 o c/w, theta-jc = 17 o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta = 0 o to +70 o c (-40 o to +85 o c for i ndustrial g rade p ackage ), v cc is 2.97v to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5v m in m ax u nits c onditions v ilck clock input low level -0.3 0.6 -0.3 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low voltage -0.3 0.8 -0.3 0.8 v v ih input high voltage 2.0 vcc 2.2 vcc v v ol output low voltage 0.4 v i ol = 5 ma 0.4 v i ol = 4 ma v oh output high voltage 2.4 v i oh = -5 ma 2.0 v i oh = -1 ma i il input low leakage current 10 10 ua i ih input high leakage current 10 10 ua c in input pin capacitance 5 5 pf i cc power supply current 3 6 ma
st16c554/554d 27 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo ac electrical characteristics ta = 0 o to +70 o c (-40 o to +85 o c for i ndustrial g rade p ackage ) , v cc is 2.97 to 5.5v, 70 p f load where applicable s ymbol p arameter l imits 3.3v 10% m in m ax l imits 5v 10% m in m ax u nit clk external clock low/high time 63 21 ns osc uart crystal/external clock frequency 8 24 mhz t as address setup time (16 mode) 5 0 ns t ah address hold time (16 mode) 5 5 ns t cs chip select width (16 mode) 80 50 ns t rd ior# strobe width (16 mode) 80 50 ns t dy read cycle delay (16 mode) 40 30 ns t rdv data access time (16 mode) 40 25 ns t dd data disable time (16 mode) 25 15 ns t wr iow# strobe width (16 mode) 35 25 ns t dy write cycle delay (16 mode) 40 30 ns t ds data setup ti me (16 mode) 20 15 ns t dh data hold time (16 mode) 5 5 ns t ads address setup (68 mode) 10 10 ns t adh address hold (68 mode) 15 15 ns t rws r/w# setup to cs# (68 mode) 10 10 ns t rda data access time (68 mode) 40 25 ns t rdh data disable time (68 mode) 25 15 ns t wds write data setup (68 mode) 20 15 ns t wdh write data hold (68 mode) 10 10 ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) 10 10 ns t csl cs# strobe width (68 mode) 80 50 ns t csd cs# cycle delay (68 mode) 40 30 ns t wdo delay from iow# to output 50 40 ns t mod delay to set interrupt from modem input 40 35 ns t rsi delay to reset interrupt from ior# 40 35 ns t ssi delay from stop to set interrupt 1 1 bclk
st16c554/554d 28 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 t rri delay from ior# to reset interrupt 45 40 ns t si delay from start to interrupt 45 40 ns t int delay from initial int reset to transmit start 8 24 8 24 bclk t wri delay from iow# to reset interrupt 45 40 ns t ssr delay from stop to set rxrdy# 1 1 bclk t rr delay from ior# to reset rxrdy# 45 40 ns t wt delay from iow# to set txrdy# 45 40 ns t srt delay from center of start to reset txrdy# 8 8 bclk t rst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate hz f igure 11. c lock t iming ac electrical characteristics ta = 0 o to +70 o c (-40 o to +85 o c for i ndustrial g rade p ackage ) , v cc is 2.97 to 5.5v, 70 p f load where applicable s ymbol p arameter l imits 3.3v 10% m in m ax l imits 5v 10% m in m ax u nit osc clk clk external clock
st16c554/554d 29 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo f igure 12. m odem i nput /o utput t iming f or c hannels a-d f igure 13. 16 m ode (i ntel ) d ata b us r ead t iming for c hannels a-d io w # io w rts# dtr# cd# cts# dsr# in t io r # ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state a ctive a ctive t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a7 cs# ior# d0-d7 rdtm t cs t rd
st16c554/554d 30 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 f igure 14. 16 m ode (i ntel ) d ata b us w rite t iming for c hannels a-d f igure 15. 68 m ode (m otorola ) d ata b us r ead t iming for c hannels a-d 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a7 cs# iow# d0-d7 t cs t wr 68read t ads t rdh t adh t csl t rda t csd t rws valid address valid address valid data a0-a7 cs# r/w# d0-d7 t rwh valid data
st16c554/554d 31 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo f igure 16. 68 m ode (m otorola ) d ata b us w rite t iming for c hannels a-d f igure 17. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d 68write t ads t adh t csl t wds t csd t rws valid address valid address valid data a0-a7 cs# r/w# d0-d7 t rwh valid data t wdh rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr)
st16c554/554d 32 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 f igure 18. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d f igure 19. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a-d tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
st16c554/554d 33 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo f igure 20. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a-d f igure 21. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a-d rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) tx txrdy# iow# int* d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit (unloading) (loading data into fifo) last data byte transmitted data in tx fifo tx fifo empty t wt t si tx fifo empty t t s isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when at least 1 byte is written to the tx fifo. t wri
st16c554/554d 34 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 f igure 22. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a-d tx txrdy# iow# int* d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit (unloading) (loading data into fifo) last data byte transmitted t si tx fifo empty t t s isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when at least 1 byte is written to the tx fifo. t wri at least 1 empty location in fifo t srt tx fifo full t wt
st16c554/554d 35 rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo package dimensions 64 lead low-profile quad flat pack (10 x 10 x 1.4 mm lqfp) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.465 0.480 11.80 12.20 d1 0.390 0.398 9.90 10.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 48 33 32 17 116 49 64 d d 1 d d 1 b e a 2 a 1 a seating plane l c
st16c554/554d 36 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 68 lead plastic leaded chip carrier (plcc) note: the control dimension is the inch column inches millimeters symbol min max min max a 0.165 0.200 4.19 5.08 a 1 0.090 0.130 2.29 3.30 a 2 0.020 ---. 0.51 --- b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.985 0.995 25.02 25.27 d 1 0.950 0.958 24.13 24.33 d 2 0.890 0.930 22.61 23.62 d 3 0.800 typ. 20.32 typ. e 0.050 bsc 1.27 bsc h 1 0.042 0.056 1.07 1.42 h 2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 1 d d 1 d d 1 d 3 d 2 a a 1 268 b a 2 b 1 e seating plane d 3 45 x h 2 45 x h 1 c r
37 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet june 2006. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. st16c554/554d rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo revision history d ate r evision d escription august 2004 3.3.0 added revision history and device status. august 2005 3.3.1 updated the 1.4mm-thick quad flat pack package description from "tqfp" to "lqfp" to be consistent wi th jedec and industry norms. april 2006 4.0.0 new datasheet format. changed active low signal designator from "-" in front of sig - nal name to "#" after signal name. updated ac electrical characteristics. june 2006 4.0.1 corrected part numbers in ordering information.
st16c554/554d i 2.97v to 5.5v quad uart with 16-byte fifo rev. 4.0.1 table of contents general description ......... ................ ................ ................. .............. .............. .......... 1 f eatures ............................................................................................................................... ..................... 1 a pplications ............................................................................................................................... ................ 1 f igure 1. st16c554 b lock d iagram ............................................................................................................................... ............ 1 f igure 2. p in o ut a ssignment ............................................................................................................................... ...................... 2 ordering information ............................................................................................................................... . 2 pin descriptions ............ ................ ................. ................ ................. ................ .......... 3 1.0 product description........................................................................................................ ............... 6 2.0 functional descriptions.................................................................................................... ........... 7 2.1 cpu interface.............................................................................................................. ................................... 7 f igure 3. st16c554 t ypical i ntel /m otorola d ata b us i nterconnections ............................................................................. 7 2.2 device reset .... .............. .............. .............. .............. .............. .............. .............. ......... .................................... 8 2.3 channel selection........... .............. .............. .............. .............. .............. .............. ........... ............................. 8 t able 1: c hannel a-d s elect in 16 m ode .............................................................................................................................. ..... 8 t able 2: c hannel a-d s elect in 68 m ode .............................................................................................................................. ..... 8 2.4 channels a-d internal registers . .............. .............. .............. .............. .............. ........... .......... ............. 9 2.5 int ouputs for channels a-d ... .............. .............. .............. .............. .............. .............. ......... ................... 9 t able 3: int p in o peration for t ransmitter for c hannels a-d ............................................................................................. 9 t able 4: int p in o peration for r eceiver for c hannels a-d ................................................................................................... 9 2.6 dma mode................................................................................................................... ....................................... 9 t able 5: txrdy# and rxrdy# o utputs in fifo and dma m ode for c hannels a-d ........................................................... 10 2.7 crystal oscillator or external clock input .......... .............. .............. ........... ........... ........... ....... 10 f igure 4. t ypical c rystal c onnections ............................................................................................................................... .... 10 2.8 programmable baud rate generator ........................................................................................... ... 10 f igure 5. b aud r ate g enerator ............................................................................................................................... ................ 11 t able 6: t ypical data rates with a 14.7456 mh z crystal or external clock ...................................................................... 11 2.9 transmitter ................................................................................................................ .................................. 11 2.9.1 transmit holding register (thr) - write only ............................................................................. .............. 11 2.9.2 transmitter operation in non-fifo mode ................................................................................... ................. 12 f igure 6. t ransmitter o peration in non -fifo m ode .............................................................................................................. 12 2.9.3 transmitter operation in fifo mode ....................................................................................... ...................... 12 f igure 7. t ransmitter o peration in fifo m ode ...................................................................................................................... 12 2.10 receiver .................................................................................................................. ..................................... 12 2.10.1 receive holding register (rhr) - read-only .............................................................................. .............. 13 f igure 8. r eceiver o peration in non -fifo m ode .................................................................................................................... 13 f igure 9. r eceiver o peration in fifo.......................................................................................................................... ............ 13 2.11 internal loopback ..... .............. .............. .............. .............. ........... ........... ........... .......... ......................... 14 f igure 10. i nternal l oop b ack in c hannel a and b ................................................................................................................ 14 3.0 uart internal registers .................................................................................................... ......... 15 t able 7: uart channel a and b uart internal registers ............................................................................ .......... 15 t able 8: internal registers description. ......................................................................................... ......................... 16 4.0 internal register descriptions............................................................................................. .. 16 4.1 receive holding register (rhr) - read- only ........... .............. .............. .............. .............. ............. .. 16 4.2 transmit holding register (thr) - write-only ............................................................................... 16 4.3 interrupt enable register (ier) - read/write.......... .............. .............. .............. .............. ............. .. 16 4.3.1 ier versus receive fifo interrupt mode operation ......................................................................... ...... 17 4.3.2 ier versus receive/transmit fifo polled mode operation .................................................................. 17 4.4 interrupt status register (isr) . ............ .............. .............. .............. .............. ............ ........... ............... 18 4.4.1 interrupt generation: .................................................................................................... .................................... 18 4.4.2 interrupt clearing: ...................................................................................................... ....................................... 18 t able 9: i nterrupt s ource and p riority l evel ....................................................................................................................... 18 4.5 fifo control register (fcr) - write-only................................................................................... ...... 19 t able 10: r eceive fifo t rigger l evel s election ................................................................................................................... 19 4.6 line control register (lcr) - read/write................................................................................... ...... 20 t able 11: p arity selection .............................................................................................................................. .......................... 21 4.7 modem control register (m cr) or general purpose output s control - read/write.. 21 t able 12: int o utput m odes .............................................................................................................................. ....................... 22 4.8 line status register (lsr) - read/write .................................................................................... ........ 22 4.9 modem status register (msr) - read/write................................................................................... ... 23
st16c554/554d ii rev. 4.0.1 2.97v to 5.5v quad uart with 16-byte fifo 4.10 scratch pad register (spr) - re ad/write .............. .............. .............. .............. ............... ............ .... 24 4.11 baud rate generator registers (dll and dlm) - read/write.......... ........... ............ ........... ..... 24 t able 13: uart reset conditions for channels a-d ................................................................................... .............. 25 absolute maximum ratings ......... ................. ................ .............. .............. ........... 26 typical package thermal resistance data (margin of error: 15%) 26 electrical characteristics....... ................. ................ .............. .............. ........... 26 dc e lectrical c haracteristics ............................................................................................................. 26 ac e lectrical c haracteristics ............................................................................................................. 27 ta = 0 o to +70 o c (-40 o to +85 o c for i ndustrial g rade p ackage ), v cc is 2.97 to 5.5v, 70 p f load where applicable ............................................................................................................................... ................. 27 f igure 11. c lock t iming ............................................................................................................................... .............................. 28 f igure 12. m odem i nput /o utput t iming f or c hannels a-d .................................................................................................... 29 f igure 13. 16 m ode (i ntel ) d ata b us r ead t iming for c hannels a-d ................................................................................... 29 f igure 14. 16 m ode (i ntel ) d ata b us w rite t iming for c hannels a-d .................................................................................. 30 f igure 15. 68 m ode (m otorola ) d ata b us r ead t iming for c hannels a-d........................................................................... 30 f igure 17. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d ............................................................ 31 f igure 16. 68 m ode (m otorola ) d ata b us w rite t iming for c hannels a-d ......................................................................... 31 f igure 18. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d .......................................................... 32 f igure 19. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a-d........................................... 32 f igure 20. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a-d............................................ 33 f igure 21. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a-d .............................. 33 f igure 22. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a-d ............................... 34 p ackage d imensions ............................................................................................................................... . 35 r evision h istory ............................................................................................................................... ...... 37 table of contents .......... ................ ................. ................ .............. .............. .............. i

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